Attending with the developments of electronic technologies, more and more high frequency electronic products are available in the market, and digital signal transmission speed also becomes faster and faster. Meanwhile, with the industrial tendency toward high frequency and high speed, some communication related issues, such as electromagnetic interference (EMI), electromagnetic compatibility (EMC), signal integrity (SI), and power integrity (PI), become significant because of the increasing of transmission speed. Thus, signal quality and integrity has become a concern of circuit design.
In detail, conventional single-ended signal lines cannot match the need of high frequency system to keep good signal integrity. Thus, most high frequency and high speed digital systems nowadays apply differential signal line pair, which has the features of common-mode noise suppression and noise interference resistance, to transmit signals. The important transmission standards, such as high definition multimedia interface (HDMI), serial advanced technology attachment (SATA), USB 3.0, PCI Express, and Thunderbolt®, have the signals transmitted by the way of differential transmission. However, asymmetrical lines in the differential signal line pair will result in time difference of the received signals, which may cause the generation of common-mode noise.
Take the transmission line on the printed circuit board of the above mentioned high frequency and high speed products as an example. FIG. 1 is a first schematic view showing a conventional transmission line structure. As shown in FIG. 1, a transmission line pair PA1 extended from a first input end (at the left hand side of the figure but not labeled) to a first output end (at the right hand side of the figure but not labeled) is composed of transmission lines PA11 and PA12 which are set on the uppermost layout layer (the first layout layer, not labeled in the figure) of the substrate PA100, the transmission line PA2 extended from a second input end (the lower side of the figure but not labeled) to a second output end (the upper side of the figure but not labeled) is set on the layout layer just below the uppermost layout layer (the second layout layer, not labeled in the figure) of the substrate PA100. That is, the transmission line pair PA1 and the transmission line PA2 are located at different layers and cross each other to form a crossing area A. The crossing area A not only generates the common-mode noise but also shows a higher capacitance to influence signal integrity.
FIG. 2 is a second schematic view showing another conventional transmission line structure. As shown in FIG. 2, a transmission line pair PA3 extended from a first input end (at the left hand side of the figure but not labeled) to a first output end (at the right hand side of the figure but not labeled) is composed of transmission lines PA31 and PA32 which are set on the uppermost layout layer (the first layout layer, not labeled in the figure) of the substrate PA200, the transmission line pair PA4 extended from a second input end (the lower side of the figure but not labeled) to a second output end (the upper side of the figure but not labeled) is composed of transmission lines PA41 and PA42 which are set on the layout layer just below the uppermost layout layer (the second layout layer, not labeled in the figure) of the substrate PA200. That is, the transmission line pair PA3 and the transmission line pair PA4 are located at different layers and cross each other to form a crossing area B. The crossing area B not only generates the common-mode noise but also shows a higher capacitance (electrical interference also exists between transmission lines PA41 and PA42) to influence signal integrity.